U.S. Pat. No. 5,959,915 to Kwon et al. discloses a method of testing an integrated circuit, such as a dynamic RAM, by doubling the applied clock frequency. The clock frequency is modified by means of a pulse generator, which may be switched between being in a doubling and in a non-doubling mode.
US patent application 2004/0041610 by Kundu discloses a DET flip-flop comprising two single-edge-triggered (SET) flip-flops responding respectively to oppositely directed transitions of the clock signal and with their outputs multiplexed according to the phases of the clock signal. The document further discloses circuitry for supporting so-called scan testing of the circuitry surrounding the flip-flop. Scan testing comprises the steps of clocking test input data into a set of flip-flops in a test mode, triggering the clock signal once in the normal mode and subsequently reading the output of the flip-flops as test output data. The disclosed circuitry comprises separate test mode clock signals for each of the SET flip-flops.
US patent application 2001/0052096 by Huijbregts discloses an SET flip-flop with circuitry for supporting scan testing.
U.S. Pat. No. 6,828,837 to Ahn discloses an SET flip-flop with a gating circuit for preventing a clock signal from triggering the flip-flop when the data input equals the data output. The purpose is to reduce the power consumed. The document further discloses providing the gated clock as a pulsed clock signal. U.S. Pat. No. 5,498,988 to Reyes et al also discloses an SET flip-flop with a gating circuit for preventing a clock signal from triggering the flip-flop when the data input equals the data output.
U.S. Pat. No. 5,719,516 to Sharpe-Geisler discloses a circuit for modifying a clock signal for a DET flip-flop. The outgoing clock signal transitions arbitrarily in synchronisation with the rising and/or falling edges of the incoming clock signal. The circuit allows selective enabling and disabling of transitions for each edge direction of the incoming clock signal.
U.S. Pat. No. 5,646,567 to Felix discloses a DET flip-flop with circuitry for supporting scan testing. The flip-flop may be switched between being in an SET and in a DET mode in order to facilitate testing.
U.S. Pat. No. 6,137,331 to Peset Llopis and U.S. Pat. No. 7,109,776 to Tschanz et al. disclose circuits for supplying a clock signal for DET circuitry, such as DET flip-flops. The circuits comprise means for disabling the clock signal output.